Power consumption management is important with battery-powered computing and/or communication devices and other devices.
Processor cores and graphics partitions consume significant amounts of power in battery-operated devices. Mobile telephones, for example, may include dual processor cores and tablet computers may include quad processor cores. Future tablet computers may include 8 or more cores. Future systems may also include increasing numbers of applications that run multiple threads to exploit the increasing numbers of processor cores. Graphics processing demands are also expected increase. Each of these factors may impact the rate of battery discharge.
A conventional mobile or battery-powered device may include an external power management IC (PMIC) to provide an off-die regulated voltage rail to a system-on-a-chip (SoC) IC to power all processor cores and a graphics processor or partition within the SoC. The off-die regulated voltage may be referred to as a PMIC VID (power power management IC voltage identification digital).
Such a shared off-die regulated voltage rail may preclude optimization of voltages provided to individual cores. Multiple off-die voltage rails may be generated from an initial off-die regulated voltage to permit per-core optimization, but at the expense of additional per-rail circuitry, such as for guard band and filtering discussed below.
An off-die regulated voltage rail may require more guard band than an on-die regulated voltage to account for variations and/or tolerance requirements in an on-die power delivery path.
An off-die regulated voltage rail may switch at a relatively low frequency, which may be less than 1 mega Hertz (Mhz). This may correspond to relatively bulky filter components having relatively long transient times, which may slow transitions between wake and sleep states of processor cores within the SoC. As a result, cores may be transitioned to a sleep state later than desired, and transitioned to a wake state sooner than necessary, resulting in less time in the sleep state.
Similar issues may arise where a graphics processor or graphics partition includes multiple execution units and memory blocks, collectively referred to herein as graphics processor elements.
Conventional voltage regulators (VRs) include switched-capacitor VRs (SCVRs) and linear VRs, such as low drop-out (LDO) VRs. A given type of VR may be relatively efficient within a designated voltage range, but may be relatively inefficient at voltages outside of the designated range. Each type of VR may include a corresponding VR controller. It may thus be impractical to implement multiple VRs and corresponding VR controllers on-die, for core and/or graphics processor element.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.